1. Field of the Invention
The present invention relates to address generators. More specifically, the present invention relates address generators for high speed buffer memories.
2. Description of the Related Art
In certain applications, there is a need to communicate a considerable amount of data at high speed. When the data can not be handled at the transmission rate, it must be buffered or stored for later processing. Conventionally, large memories are used to provide a data buffer and several processors are used to feed data to the buffer memory. A priority scheme is then used to arbitrate access to the shared memory. At one time, each processor had its own pointer to memory. The pointer was implemented as a memory address stored in a register or a section of memory and used for reads or writes of data to memory. Unfortunately, the use of multiple pointers was found to be somewhat expensive. Accordingly, a scheme was developed by which the processors accessed the shared memory using a single pointer. Whether a read pointer or a write pointer is used, the pointer must be incremented to permit subsequent reads or writes.
The single pointer scheme works well so long as one processor is not granted access to the memory during successive clock cycles. When a single processor is granted access during successive read or write cycles, there is no time to increment the pointer due to the fact that the processor is ready for the memory access in a shorter time frame than would be the case if a different processor was granted access.
Hence, there is a need in the art for a system and technique for providing for access to a shared memory by a single processor during successive read or write cycles.